PIC18C658T-I/L【PDF 56/246 页】IC MCU OTP 16KX16 CAN 68PLCC

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2000 Microchip Technology Inc.

Advanced Information

DS30475A-page 149

PIC18CXX8

15.4.1.2

Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overflow condition exists, then

no acknowledge (ACK) pulse is given. An overflow con-

dition is defined as either bit BF (SSPSTAT register) is

set or bit SSPOV (SSPCON1 register) is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR registers) must be cleared in

software. The SSPSTAT register is used to determine

the status of the byte.

15.4.1.3

Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3/SCK/SCL is held

low. The transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR regis-

ter. Then pin RC3/SCK/SCL should be enabled by set-

ting bit CKP (SSPCON1 register). The master must

monitor the SCL pin prior to asserting another clock

pulse. The slave devices may be holding off the master

by stretching the clock. The eight data bits are shifted

out on the falling edge of the SCL input. This ensures

that the SDA signal is valid during the SCL high time

(Figure 15-8).

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

As a slave-transmitter, the ACK pulse from the

master-receiver is latched on the rising edge of the

ninth SCL input pulse. If the SDA line is high (not ACK),

then the data transfer is complete. When the ACK is

latched by the slave, the slave logic is reset (resets

SSPSTAT register) and the slave monitors for another

occurrence of the START bit. If the SDA line was low

(ACK), the transmit data must be loaded into the SSP-

BUF register, which also loads the SSPSR register. Pin

RC3/SCK/SCL should be enabled by setting bit CKP.

FIGURE 15-7: I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

FIGURE 15-8: I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

A7 A6 A5 A4 A3 A2 A1

SDA

SCL

456

Bus Master

Terminates

Transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK

Receiving Data

ACK

R/W=0

Receiving Address

SSPIF

SSPOV

Not ACK

ACK is not sent.

SDA

SCL

SSPIF

CKP

ACK

Not ACK

Transmitting Data

R/W = 1

Receiving Address

789

123

Cleared in software

SSPBUF is written in software

From SSP interrupt

service routine

Set bit after writing to SSPBUF

Data in

Sampled

SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written to

before the CKP bit can be set)

R/W = 0

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